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1 features ? 2nd generation ee complex programmable logic devices ? 3.0v to 3.6v operating range with i/os 3.3 or 5v compliant ? 32 - 512 macrocells with enhanced features ? pin-compatible with industry-standard devices ? speeds to 5 ns maximum pin-to-pin delay ? registered operation to 225 mhz enhanced macrocells with logic doubling ? features ? bury either register or com while using the other for output ? dual independent feedback allows multiple latch functions per macrocell ? 5 product terms per macrocell, expandable to 40 per macrocell with cascade logic, plus 15 more with foldback logic ? d/t/latch configurable flip-flops plus transparent latches ? global and/or per macrocell register control signals ? global and/or per macrocell output enable ? programmable output slew rate per macrocell ? programmable output open collector option per macrocell ? fast registered input from product term enhanced connectivity ? single level switch matrix for maximum routing options ? up to 40 inputs per logic block advanced power management features ? itd (input transition detection) available individually on global clocks, inputs and i/o for a level standby current on ? l ? versions ? pin-controlled 1 ma standby mode ? reduced-power per macrocell ? automatic power down of unused macrocells ? programmable pin-keeper inputs and i/os available in commercial and industrial temperature ranges available in all popular packages including plcc, pqfp, tqfp and bga ee technology ? 100% tested ? completely reprogrammable ? 10,000 program/erase cycles ? 20 year data retention ? 2000v esd protection ? 200 ma latch-up immunity jtag boundary-scan testing port per ieee 1149.1-1990 and 1149.1a-1993 ? pull-up option on jtag pins tms and tdi ieee 1532 compatibility for fast in-system programmability (isp) via jtag pci-compliant security fuse feature atf15xxae family datasheet atf1502ae(l) atf1504ae(l) atf1508ae(l) atf1516ae(l) atf1532ae(l) preliminary rev. 2398b ? 08/01
2 atf15xxae family 2398b ? 08/01 44-lead tqfp ? top view 44-lead plcc ? top view 1 11 33 23 44 34 12 22 atf1502ae(l) atf1504ae(l) 12 39 34 6 1 18 23 28 atf1502ae(l) atf1504ae(l) 84-lead plcc ? top view 22 32 64 54 11 1 75 43 atf1508ae(l)
3 atf15xxae family 2398b ? 08/01 100-lead tqfp ? top view 144-lead tqfp ? top view 1 13 25 75 63 100 88 38 50 atf1504ae(l) atf1508ae(l) atf1516ae(l) 1 19 36 108 90 144 127 54 72 atf1508ae(l) atf1516ae(l) atf1532ae(l) 208-lead pqfp ? top view 1 26 156 131 208 183 53 78 104 atf1516ae(l) atf1532ae(l)
4 atf15xxae family 2398b ? 08/01 atf1504ae(l) 49-ball 0.8 mm pitch bottom view atf1508ae(l) 169-ball 0.8 mm pitch bottom view atf1504ae(l) atf1508ae(l) atf1516ae(l) 100-ball 1.0 mm pitch bottom view atf1508ae(l) atf1516ae(l) atf1532ae(l) 256-ball 1.0 mm pitch bottom view a b c d e f g 7 654321 a b c d e f g h j k l m n 13 121110987654321 a b c d e f g h j k 10 987654321 a b c d e f g h j k l m n p r t 16 151413121110987654321
5 atf15xxae family 2398b ? 08/01 general description beginning with the introduction of the 100% connected atf1500 with 32 enhanced macrocells in 1996, atmel ? s cpld products have delivered extra io connectivity and logic reusability. atmel ? s commitment to efficient, flexible architecture has continued with the current atmel atf15xx family of industry-standard, pin-compatible cplds. atmel ? s logic doubling archi- tecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend cpld place and route efficiency. atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller cpld or leave spare room for later revisions. the atmel atf15xx family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective. the atmel atf15xx family includes all popular configurations and speeds. the atmel atf15xxae family includes pin-compatible products in all popular packages. notes: 1. contact atmel for up-to-date information on device and package availability. 2. when the jtag port is used for in system programming (isp) or boundary-scan testing (bst), the four associated pins become jtag pins and are unavailable for user i/o. 3. thermal analysis must be performed for this package to ensure compliance with dc and ac operating conditions. for more information, see ? thermal characteristic ? s of atmel packages ? . table 1. atf15xxae family device features feature atf1502ae(l) atf1504ae(l) atf1508ae(l) atf1516ae(l) atf1532ae(l) usable gates 625 1250 2500 5000 10000 macrocells 32 64 128 256 512 logic blocks 2481632 max. # pins 44 100 256 256 256 max. user i/os 36 68 100 164 212 t pd grades (ns) 4, 7, 10(15) 4, 7, 10(15) 5, 7, 10(15) 5, 7, 10(15) 5, 7, 12(15) table 2. atf15xxae family device packages and number of signal pins (1)(2) packages atf1502ae(l) atf1504ae(l) atf1508ae(l) atf1516ae(l) atf1532ae(l) 44-pin plcc 36 36 44-pin tqfp 36 36 49-ball bga 41 84-pin plcc 68 100-pin tqfp 68 84 (3) 84 100-ball bga 68 84 84 144-pin tqfp 100 120 120 169-ball bga 100 208-pin pqfp 164 176 256-ball bga 100 164 212
6 atf15xxae family 2398b ? 08/01 functional description the atf15xxae family of 3.3 volt supply, high-performance, high-density complex program- mable logic devices (cplds) utilizes atmel ? s proven electrically-erasable technology. with up to 512 macrocells, they easily integrate logic from several ttl, ssi, msi, lsi and classic plds. the atf15xxae family ? s enhanced macrocell architecture, switch matrices and routing increase usable gate count for new designs and increase odds of successful pin-locked design modifications while maintaining pin-compatibility with industry-standard cplds. the atf15xxae family devices have four dedicated input pins and depending on the type of device and package, up to 208 bi-directional i/o pins. each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. each input and i/o pin also feeds into the global bus. the macrocells are organized into groups of sixteen called logic blocks. the switch matrix in each logic block selects 40 individual signals from the global bus. macrocells within a given logic block may share their sixteen foldback signals on a regional foldback bus. cascade logic between macrocells in the logic block allows fast, efficient generation of complex logic func- tions. all macrocells are capable of being i/os; however, the actual number of i/o pins depends on the device and package type. the atf15xxae family members contain two, four, eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a fan-in of 40 inputs from the switch matrix having access to up to 80 product terms. unused macrocells are automatically disabled by the fitter software to decrease power con- sumption. a security fuse, when programmed, protects the contents of the other fuses. two bytes (16 bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. the atf15xxae family devices are in-system programmable (isp) devices. they use the industry-standard 4-pin jtag interface (ieee std. 1149.1), and are fully-compliant with jtag ? s boundary-scan description language (bsdl). isp allows the device to be pro- grammed without removing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software. global bus/switch matrix the global bus (figure 1) contains all input and i/o pin signals as well as the buried feedback signals from all macrocells. the switch matrix in each logic block receives as its inputs all sig- nals from the global bus. up to 40 of these signals can be selected as inputs to the individual logic blocks by the fitter software. atmel ? s atf15xx family of cplds use a single level switch matrix signal distribution structure, where each logic block input has access to the same num- ber of global bus inputs, maximizing the number of possible ways to route a global bus signal. this single level structure is in contrast with split switch matrix structures used by others in which routing a particular global bus input to a particular logic block input makes that signal unavailable to some other logic blocks, thus greatly limiting the available opportunities to route. the atf15xxae family macrocell, shown in figure 2, consists of five sections: product terms and product term select multiplexer, or/xor/cascade logic, foldback bus, a flip-flop and output buffer. extra fan-in and signal routing are provided throughout. each macrocell can generate a foldback logic term from the product term mux and a buried feedback with extra routing that go to the global bus.
7 atf15xxae family 2398b ? 08/01 figure 1. atf15xxae family typical block diagram 2 to 16 n n-1 2 to 16
8 atf15xxae family 2398b ? 08/01 figure 2. atf15xxae family macrocell with enhanced features in red product terms and select mux within each macrocell are five product terms. each product term may receive as its inputs any combination of the signals from the switch matrix or regional foldback bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is determined by the fitter software, which selects the optimum macrocell configuration. or/xor/ cascade logic within a single macrocell, all the product terms can be routed to the or gate, creating a 5- input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. the macrocell ? s xor gate allows efficient implementation of compare and arithmetic func- tions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high- or low-level. for combinatorial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimiza- tion of product terms. the xor gate may be fed from the flip-flop output to emulate t- and jk- type flip-flops, or fed to the buried feedback to synthesize an extra latch. foldback bus each macrocell can also generate a foldback product term. this signal goes to the regional bus and is available to the 16 macrocells in a given logic block. the foldback is an inverse polarity of one of the macrocell ? s product terms. although cascade logic is the preferred method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms in each region can also generate additional fan-in sum terms with nominal additional delay. regional foldback bus 16 logic foldback i/o pin 3 gck[0:2] gclear casout d/ t*/l ce ar ap q casin i/o pin slew rate open collector 6 goe[0:5] reduced power option s w i t c h m a t r i x 80 global bus 40 1 2 3 4 5 p r o d u c t t e r m m u x pt1 pt2 pt3 pt5 pt4 switch matrix outputs * t flip-flop synthesised !q q !q ck/ck /le goe switch matrix goe [0:5]
9 atf15xxae family 2398b ? 08/01 flip-flop the atf15xxae family ? s flip-flop has very flexible data and control functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output or vice-versa. (this enhanced function is automatically implemented by the fitter software). the flip-flop can be configured for d, t, jk and sr operation, and changes state on the clock ? s rising edge. it can also be configured as a flow-through latch. in this mode, data passes through when the clock is high and is latched when the clock is low. when a gck signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip-flop has asynchronous reset and preset. the flip-flop ? s asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a product term. the asynchro- nous preset (ap) can be a product term or always off. output buffer the atf15xxae family macrocell output can be selected as registered or combinatorial. the extra buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. (this enhanced function is automatically implemented by the fitter software) feedback of a buried combinatorial output allows the cre- ation of a second latch within a macrocell. the output enable multiplexer (moe) controls the output enable signals. any buffer can be permanently enabled for simple output operation. buffers can also be permanently disabled to allow use of the pin as an input. in this configuration, all the macrocell resources are still avail- able, including the buried feedback, expander and cascade logic. the output enable for each macrocell can be selected as one of six global oe signals or a product term. in addition, some product term feedbacks can generate one of the global output enables. the buffer has a fast/slow slew rate option to control emi and an open-collector option which enables the device to provide control signals such as an interrupt that can be asserted by any of the several devices. programmable pin-keeper option for inputs and i/os the atf15xxae family offers the option of programming all input and i/o pins with pin-keeper circuits enabled. when any pin is driven high or low and then subsequently left floating, the pin keeper circuit will hold it at that previous high or low-level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the pin-keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption.
10 atf15xxae family 2398b ? 08/01 input diagram i/o diagram speed/power management the atf15xxae family has several speed and power management features. multiple power supplies, power sequencing and hot-socketing the table below summarizes the allowable power supply voltages for the atf15xxae family. because the atf15xxae family can be used in a system with mixture of power supply volt- ages, it has been designed to function with the v ccint and v ccio power supplies applied in any sequence. also, until the power up sequence completes, the input/output buffers are kept in a high impedance state, and so may be driven but do not drive power out. programmable option (pin keeper) programmable option (pin keeper) external and internal supply voltage v ccint = 3.3v v ccio = 3.3v yes v ccio = 5.0v yes
11 atf15xxae family 2398b ? 08/01 power-on reset the atf15xx family devices are designed with a power-on reset, a feature critical for state machine initialization. at a point delayed slightly from v cc crossing v rst , all registers will be initialized, and the state of each output will depend on the polarity of its buffer. however, due to the asynchronous nature of reset and uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. the clock must remain stable during t d . the atf15xx family has two options for the hysteresis about the reset level, v rst , small and large. to ensure a robust operating environment in applications where the device is operated near 3.0v, atmel recommends that during the fitting process users configure the device with the power-on reset hysteresis set to large. power down of unused macrocells to conserve power, atmel fitters automatically power down all unused macrocells. input transition detection/ automatic power down in addition, the atf15xxae(l) devices contain itd (input transition detection) circuits on global clocks, inputs and i/o. when activated, itd automatically puts the device into a low- power standby mode when no logic transitions are occurring. this reduces power consump- tion during inactive periods, and therefore also provides proportional power-savings for most applications running at system speeds below 5 mhz. reduced-power per macrocell to further reduce power, each atf15xx family macrocell has a reduced-power bit feature. with this feature the designer can reduce power by 50% or more for logic that does not need to operate at the maximum switching speed. the reduced-power bit may be activated by changing the default off to on for any or all macrocells. for macrocells in reduced-power mode (reduced-power bit turned on), the reduced- power adder, t rpa , must be added to the ac parameters, which include the data paths t lad , t lac , t ic , t acl , t ach and t sexp . all power-down ac characteristic parameters are computed from external input or i/o pins, with the reduced- power bit turned on. slew rate control each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching. the slew rate option is selected in the design source file. pin controlled power-down all atf15xx family devices also have an optional pin-controlled power-down mode. when activated, one or both of two pins, pd1 and pd2, can act as power-down pins. the device goes into power-down when either pd1 or pd2 pins (or both) are high, and the device supply current is reduced to less than 1 ma. also, all internal logic signals are latched and held, as are any enabled outputs. therefore, all registered and combinatorial output data remain valid. any outputs that were in a high-z state at the onset will remain at high-z. input and i/o hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. all pin transitions are ignored until the pd pin is brought low. when the power- down feature is enabled for pd1 or pd2, that pin cannot be used as a logic input or output. however, the pin ? s macrocell may still be used to generate buried foldback and cascade logic signals. the power-down option is selected in the design source file.
12 atf15xxae family 2398b ? 08/01 power consumption estimates an estimate of power consumption can be made based on typical designs and operation con- ditions, but because it is sensitive to these factors, power consumption must be verified with actual pattern and operation conditions. the equations given below are based on a pattern of 16-bit up/down counters in each logic block and may be used to estimate power consumption for both operating modes. standby power 1. p standby = i ccstandby x v supply where: i ccstandby = the standby current given for the particular device and standby mode (eg pin con- trolled power down) v supply = the power supply voltage active power 2. p active = p internal + p load = i ccinternal x v supply + p load where: i ccinternal = the internal current estimated from equation 3 below v supply = the power supply voltage p load = depends on the device output load capacitance and switching frequency on each out- put pin. p load and additional power savings at low frequencies using atmel input transition detection ( ? l ? versions) can be estimated according to the methods discussed in the atmel application note ? saving power with atmel plds ? 3. i ccinternal = [k 1 x (mc inuse ? mc reducedpower )] + (k 2 x mc reducedpower ) + (k 3 x mc inuse x f op x ns) where: mc reducedpower = the number of macrocells operating at reduced power (from fitter report file) mc inuse = the number of macrocells in use (from fitter report file. unused macrocells are pow- ered down.) ns = the proportion of logic nodes switching (typically 10-20 %) f op = the switching frequency k 1 , k 2, and k 3 = device constants given in the table below. note: shaded data is preliminary and subject to change without notice. device k 1 k 2 k 3 atf1502ae 0.6 0.3 0.015 atf1504ae 0.6 0.3 0.015 atf1508ae 0.6 0.3 0.015 atf1516ae 0.6 0.3 0.015 atf1532ae 0.6 0.3 0.015
13 atf15xxae family 2398b ? 08/01 design software atmel atf15xx family fitters allow logic synthesis using a variety of high-level description lan- guages and formats. atf15xx family designs are supported by atmel specific design tools as well as by several third-party tools. free conversion software is also offered for industry stan- dard devices. check the atmel web site or contact your authorized atmel sales representative for up-to-date design software information. programming atf15xx family devices can be programmed using standard third-party programmers. with third-party programmers, the jtag isp port can be disabled thereby allowing four additional i/o pins to be used for logic. check the atmel web site, contact your authorized atmel sales representative or atmel pld applications for details of third-party programmers. atf15xx family devices are in-system programmable (isp) devices utilizing the 4-pin jtag protocol. this capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. atmel provides isp hardware and soft- ware to allow programming of the atf15xx family via the pc. isp is performed by using either a download cable, a compatible board tester or a simple microprocessor interface. it is most common to devote the jtag pins to isp, but it is possible to use isp to program the part through the jtag pins, and set these four pins i/o pins. however, this will effectively dis- able further isp and the device will need to be erased on a programmer to re-enable isp. contact atmel pld applications by email at pld@atmel.com or call our hotline at (408) 436- 4333 for details. to allow isp programming support by the automated test equipment (ate) vendors, serial vector format (svf) files can be created by the atmel isp software. conversion to other ate tester formats is also possible. check the atmel web site for up-to-date programming and soft- ware support information. isp programming protection the atf15xx family also incorporates a protection feature that locks the device and prevents the inputs and i/o from driving if the programming process is interrupted for any reason. the inputs and i/o default to high-z state during such a condition. in addition the pin-keeper option preserves the former state during device programming. all atf15xx family devices are initially shipped in the erased state thereby making them ready to use for isp. for more information refer to the ? designing for in-system programmability with atmel cplds ? application note. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf15xx family fuse pat- terns. once programmed, fuse verify is inhibited. however, the user signature and device id remain accessible.
14 atf15xxae family 2398b ? 08/01 jtag-bst overview the jtag-bst (jtag boundary-scan testing) is controlled by the test access port (tap) controller. the boundary-scan technique involves the inclusion of a shift-register stage (con- tained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. each input pin and i/o pin has its own boundary-scan cell (bsc) in order to support boundary-scan testing. the atf15xxae family does not currently include a test reset (trst) input pin because the tap controller is automatically reset at power-up. the atf15xx family implements six bst instruc- tions, and seven atmel-defined in system programming (isp) instructions. all atf15xx family bst and isp instructions have a length of 10 bits. the atf15xx family bst implementation complies with the boundary-scan definition lan- guage (bsdl) described in the jtag specification (ieee standard 1149.1). any third-party tool that supports the bsdl format can be used to perform bst on the atf15xx family. the atf15xx family also has the option of using four jtag-standard i/o pins for in-system programming (isp). the atf15xx family is programmable through the four jtag pins using programming-compatible with the ieee jtag standard 1149.1. programming is performed by using 5v ttl-level programming signals from the jtag isp interface. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are available as i/o pins. refer to atmel application note ? designing for in-system programma- bility with atmel cplds for more details. jtag bst instructions description sample/preload captures signals at the device pins for later examination, or loads a data pattern prior to an extest instruction. extest allows testing of off-chip circuitry and interconnections by forcing a pattern on the output pins or capturing signals from the input pins. bypass places a single shift register stage between tdi and tdo, allowing test bst data to pass through a particular device in a chain of devices. idcode places the 32-bit idcode register between tdi and tdo, allowing the idcode data to be shifted out of tdo. uescode places the 16-bit user electronic signature register between tdi and tdo, allowing the uescode data to be shifted out of tdo. highz places the bypass register between tdi and tdo in a high impedance mode, protecting the device from damage from externally applied test signals. 7 isp instructions these seven instructions allow in-system programming via the four jtag pins.
15 atf15xxae family 2398b ? 08/01 jtag boundary-scan cell (bsc) testing the atf15xx family has four dedicated input pins and a number of i/o pins depending on the device type and package type selected. each input pin and i/o pin has a boundary-scan cell (bsc) which supports boundary-scan testing as described in detail by ieee standard 1149.1. a typical bsc consists of three capture registers or scan registers and up to two update regis- ters. there are two types of bscs, one for input or i/o pin, and one for the macrocells. the bscs in the device are chained together through the (bst) capture registers. input to the cap- ture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. control signals are generated internally by the jtag tap controller. note: shaded data is preliminary and subject to change without notice. boundary-scan definition language (bsdl) models these are now available in all package types via the atmel web site. these models conform to the ieee 1149.1 standard and can be used for boundary-scan test operation of the atf15xx family. the bsc configuration for the input and i/o pins and macrocells are shown below. device boundary-scan register length idcode msb lsb atf1502ae 96 0000,0001,0101,0100,0010,0000,0011,1111 atf1504ae 192 0000,0001,0101,0100,0100,0000,0011,1111 atf1508ae 352 0000,0001,0101,0100,1000,0000,0011,1111 atf1516ae 672 0000,0001,0101,0101,0000,0000,0011,1111 atf1532ae 1232 0000,0001,0101,0110,0000,0000,0011,1111
16 atf15xxae family 2398b ? 08/01 bsc configuration for pins (except jtag tap pins) . bsc configuration for macrocell 0 1 0 1 dq dq capture register update register 0 1 0 1 dq dq tdi outj oej shift clock mode tdo macrocell bsc pin
17 atf15xxae family 2398b ? 08/01 pci compliance the atf15xx family also supports peripheral component interconnect (pci) interface stan- dard in pci-based designs and specifications. the pci interface calls for high current drivers, which are much larger than the traditional ttl drivers. pci voltage-to- current curves for +5v signaling in pull-up mode pci voltage-to- current curves for +5v signaling in pull-down mode 2.4 vcc 1.4 -2 -44 -178 current (ma) ac drive point dc drive point voltage pull up test point 2.2 vcc 0.55 3.6 95 380 current (ma) ac drive point dc drive point voltage pull down test point
18 atf15xxae family 2398b ? 08/01 note: 1. junction temperature is package and device dependant and can be calculated as follows: t j(max) = t a(max) + ( ja | air flow = 0 *p (max) ). for more information, see ? thermal characteristic ? s of atmel packages ? . note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. input test waveforms and measurement levels output ac test loads dc and ac operating conditions commercial industrial operating temperature (ambient), t a 0 c - 70 c-40 c - 85 c junction temperature, t j (1) ?? v cc (3.3v) power supply 3.0v - 3.6v 3.0v - 3.6v pin capacitance typ (1) max units condition c in 8pfv in = 0v; f = 1.0 mhz c i/o 8pfv out = 0v; f = 1.0 mhz 3.0v 703 8060
19 atf15xxae family 2398b ? 08/01 timing model absolute maximum ratings* ambient temperature under bias.................. -65 c to +135 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. for currents less than 100 ma, minimum voltage is -0.6 vdc and maximum voltage is v cc + 0.75 vdc. pulses of less than 20s may under- shoot to -2.0v or overshoot to 5.75v. storage temperature ..................................... -65 c to +150 c junction temperature ..............................................150 c (max) voltage on any pin with respect to ground .......................................-2.0v to +5.75v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) dc output current per pin ................................ -25 to +25 ma u
20 atf1502ae(l) 2398b ? 08/01 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. dc characteristics atf1502ae(l) (1) symbol parameter condition min typ min unit i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 2 10 a i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 40 ma ind. 45 ma ? itd ? mode com. 1 ma ind. 1 ma i cc2 power supply current, power-down mode v cc = max v in = 0, v cc pd mode 0.1 1 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std mode com. 25 ma ind. 30 ma v il input low voltage -0.3 0.8 v v ih input high voltage 1.7 v ccio +0.3 v v ol output low voltage (ttl) v in = v ih or v il v cc = min, i ol = 8 ma com. 0.45 v ind. 0.45 v output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage -3.3v (ttl) v in = v ih or v il v cc = min, i oh = -2.0 ma 2.4 v output high voltage -3.3v (cmos) v in = v ih or v il v cc = min, i oh = -0.1 ma v ccio -0.2 v power-down ac characteristics atf1502ae(l) (1) symbol parameter -4 -7 -10 -15 unit min max min max min max min max t ivdh valid 1, i/o before pd high 4.5 7.5 10 15 ns t gvdh valid 1, oe (2) before pd high 4.5 7.5 10 15 ns t cvdh valid 1, clock (2) before pd high 4.5 7.5 10 15 ns t dhix i, i/o don ? t care after pd high 9.0 15 20 25 ns t dhgx oe (2) don ? t care after pd high 9.0 15 20 25 ns t dhcx clock (2) don ? t care after pd high 9.0 15 20 25 ns t dliv pd low to valid i, i/o 1.0 1.0 1.0 1.0 s t dlgv pd low to valid oe, (pin or term) 1.0 1.0 1.0 1.0 s t dlcv pd low to valid clock, (pin or term) 1.0 1.0 1.0 1.0 s t dlov pd low to valid output 1.0 1.0 1.0 1.0 s
21 atf1502ae(l) 2398b ? 08/01 ac characteristics (1) atf1502ae(l) symbol parameter -4 -7 -10 -15 unit min max min max min max min max t pd1 input or feedback to non-registered output 4.5 7.5 10 15 ns t pd2 i/o input or feedback to non-registered feedback 4.5 7.5 10 12 ns t su global clock setup time 2.9 4.7 6.3 11 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold of fast input 0.0 0.0 0.0 1.0 mhz t cop global clock to output delay 1.0 3.0 1.0 5.0 1.0 6.7 1.0 8.0 ns t ch global clock high time 2.0 3.0 4.0 5.0 ns t cl global clock low time 2.0 3.0 4.0 5.0 ns t asu array clock setup time 1.6 2.5 3.6 4.0 ns t ah array clock hold time 0.3 0.5 0.5 4.0 ns t acop array clock output delay 1.0 4.3 1.0 7.2 1.0 9.4 1.0 15 ns t ach array clock high time 2.0 3.0 4.0 6.0 ns t acl array clock low time 2.0 3.0 4.1 6.0 ns t cnt minimum clock global period 4.4 7.2 9.7 13 ns f cnt maximum internal global clock frequency 225 135 100 77 mhz t acnt minimum array clock period 4.4 7.2 9.7 13 ns f acnt maximum internal array clock frequency 225 135 100 77 mhz f max maximum clock frequency 230 140 100 77 mhz t in input pad and buffer delay 0.7 1.2 1.5 2.0 ns t io i/o input pad and buffer delay 0.7 1.2 1.5 2.0 ns t fin fast input delay 2.3 2.8 3.4 2.0 ns t sexp foldback term delay 1.9 3.1 4.0 8.0 ns t pexp cascade logic delay 0.5 0.8 1.0 1.0 ns t lad logic array delay 1.5 2.5 3.3 6.0 ns t lac logic control delay 0.6 1.0 1.2 3.5 ns t ioe internal output enable delay 0.0 0.0 00 3.0 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 0.8 1.3 1.8 3.0 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l =35pf) 1.3 1.8 2.3 3.0 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 5.8 6.3 6.8 5.0 ns
22 atf1502ae(l) 2398b ? 08/01 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac , t ic , t acl and t sexp parameters for macrocells running in the reduced- power mode. t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 4.0 4.0 5.0 7.0 ns t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l =35pf) 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5v or 3.3v; c l = 35pf) 9.0 9.0 10.0 10 ns t xz output buffer disable delay (c l = 5pf) 4.0 4.0 5.0 6.0 ns t su register setup time 1.3 2.0 2.8 4.0 ns t h register hold time 0.6 1.0 1.3 4.0 ns t fsu register setup time of fast input 1.0 1.5 1.5 2.0 ns t fh register hold time of fast input 1.5 1.5 1.5 2.0 ns t rd register delay 0.7 1.2 1.5 2.0 ns t comb combinatorial delay 0.6 1.0 1.3 2.0 ns t ic array clock delay 1.2 2.0 2.5 7.0 ns t en register enable time 0.6 1.0 1.2 7.0 ns t glob global control delay 0.8 1.3 1.9 1.0 ns t pre register preset time 1.2 1.9 2.6 5.0 ns t clr register clear time 1.2 1.9 2.6 5.0 ns t uim switch matrix delay 0.9 1.5 2.1 2.0 ns t rpa (2) reduced power adder 2.5 4.0 5.0 14 ns ac characteristics (1) atf1502ae(l) (continued) symbol parameter -4 -7 -10 -15 unit min max min max min max min max
23 atf1502ae(l) 2398b ? 08/01 stand-by i cc vs. supply voltage (t a = 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.8 5.0 5.3 5.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. supply voltage (v oh = 2.4v) -50 -40 -30 -20 -10 0 4.0 4.5 5.0 5.5 6.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol = 0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc = 5.0v, t a = 25 c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc = 5.0v, t a = 25 c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd
24 atf1502ae(l) 2398b ? 08/01 input clamp current vs. input voltage (v cc = 5.0v, t a = 35 c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc = 5.0v, t a = 25 c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input current (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd
25 atf1502ae(l) 2398b ? 08/01 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd
26 atf1502ae(l) 2398b ? 08/01 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gndint ground pins for the internal device logic gndio ground pins for the i/o drivers vccint vcc pins for the internal device logic (+3.3v) vccio vcc for the i/o drivers atf1502ae(l) dedicated pinouts dedicated pin 44-lead j-lead 44-lead tqfp input/oe2/gclk2 2 40 input/gclr 1 39 input/oe1 44 38 input/gclk1 43 37 i/o/gclk3 41 35 i/o/pd (1,2) 11, 25 5, 19 i/o/tdi (jtag) 7 1 i/o/tms (jtag) 13 7 i/o/tck (jtag) 32 26 i/o/tdo (jtag) 38 32 gndint 22, 42 16, 36 gndio 10, 30 4, 24 vccint 3, 23 17, 41 vccio 15, 35 9, 29 # of signal pins 36 36 # user i/o pins 32 32
27 atf1502ae(l) 2398b ? 08/01 atf1502ae(l) i/o pinouts mc plc 44-lead plcc 44-lead tqfp 1a442 2a543 3a644 4/ tdi a71 5a82 6a93 7/ pd1 a115 8a126 9/ tms a137 10 a 14 8 11 a 16 10 12 a 17 11 13 a 18 12 14 a 19 13 15 a 20 14 16 a 21 15 17 b 41 35 18 b 40 34 19 b 39 33 20/ tdo b3832 21 b 37 31 22 b 36 30 23 b 34 28 24 b 33 27 25/ tck b3226 26 b 31 25 27 b 29 23 28 b 28 22 29 b 27 21 30 b 26 20 31/ pd2 b2519 32 b 24 18
28 atf1502ae(l) 2398b ? 08/01 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use commercial product for industrial temperature ranges, de-rate i cc by 15%. atf1502ae(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 4 3 230 atf1502ae-4 ac44 atf1502ae-4 jc44 44a 44j commercial (0 c to 70 c) 7 5 140 atf1502ae-7 ac44 atf1502ae-7 jc44 44a 44j commercial (0 c to 70 c) atf1502ae-7 ai44 atf1502ae-7 ji44 44a 44j industrial (-40 c to +85 c) 10 6.7 100 atf1502ae-10 ac44 atf1502ae-10 jc44 44a 44j commercial (0 c to 70 c) atf1502ae-10 ai44 atf1502ae-10 ji44 44a 44j industrial (-40 c to +85 c) 15 8 77 atf1502ael-15 ac44 atf1502ael-15 jc44 44a 44j commercial (0 c to 70 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc)
29 atf1504ae(l) 2398b ? 08/01 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. dc characteristics (1) atf1504ae(l) symbol parameter condition min typ min unit i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 2 10 a i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 60 ma ind. 75 ma ? itd ? mode com. 1 ma ind. 1 ma i cc2 power supply current, power-down mode v cc = max v in = 0, v cc pd mode 0.1 1 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std mode com. 55 ma ind. 80 ma v il input low voltage -0.3 0.8 v v ih input high voltage 1.7 v ccio +0.3 v v ol output low voltage (ttl) v in = v ih or v il v cc = min, i ol = 8 ma com. 0.45 v ind. 0.45 v output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage -3.3v (ttl) v in = v ih or v il v cc = min, i oh = -2.0 ma 2.4 v output high voltage -3.3v (cmos) v in = v ih or v il v cc = min, i oh = -0.1 ma v ccio -0.2 v power-down ac characteristics (1) atf1504ae(l) symbol parameter -4 -7 -10 -15 unit minmaxminmaxminmaxminmax t ivdh valid 1, i/o before pd high 4.5 7.5 10 15 ns t gvdh valid 1, oe (2) before pd high 4.5 7.5 10 15 ns t cvdh valid 1, clock (2) before pd high 4.5 7.5 10 15 ns t dhix i, i/o don ? t care after pd high 9.0 15 20 25 ns t dhgx oe (2) don ? t care after pd high 9.0 15 20 25 ns t dhcx clock (2) don ? t care after pd high 9.0 15 20 25 ns t dliv pd low to valid i, i/o 1.0 1.0 1.0 1.0 s t dlgv pd low to valid oe, (pin or term) 1.0 1.0 1.0 1.0 s t dlcv pd low to valid clock, (pin or term) 1.0 1.0 1.0 1.0 s t dlov pd low to valid output 1.0 1.0 1.0 1.0 s
30 atf1504ae(l) 2398b ? 08/01 ac characteristics atf1504ae(l) (1) symbol parameter -4 -7 -10 -15 unit min max min max min max min max t pd1 input or feedback to non-registered output 4.5 7.5 10 15 ns t pd2 i/o input or feedback to non-registered feedback 4.5 7.5 10 12 ns t su global clock setup time 2.8 4.7 6.2 11 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold of fast input 0.0 0.0 0.0 1.0 mhz t cop global clock to output delay 1.0 3.1 1.0 5.1 1.0 7.0 1.0 9.0 ns t ch global clock high time 2.0 3.0 4.0 5.0 ns t cl global clock low time 2.0 3.0 4.0 5.0 ns t asu array clock setup time 1.6 2.6 3.6 5.0 ns t ah array clock hold time 0.3 0.4 0.6 4.0 ns t acop array clock output delay 1.0 4.3 1.0 7.2 1.0 9.6 1.0 15 ns t ach array clock high time 2.0 3.0 4.0 6.0 ns t acl array clock low time 2.0 3.0 4.0 6.0 ns t cnt minimum clock global period 4.5 7.4 10 13 ns f cnt maximum internal global clock frequency 225 135 100 77 mhz t acnt minimum array clock period 4.5 7.4 10 13 ns f acnt maximum internal array clock frequency 225 135 100 77 mhz f max maximum clock frequency 230 140 100 77 mhz t in input pad and buffer delay 0.6 1.1 1.4 2.0 ns t io i/o input pad and buffer delay 0.6 1.1 1.4 2.0 ns t fin fast input delay 2.5 3.0 3.7 2.0 ns t sexp foldback term delay 1.8 3.0 3.9 8.0 ns t pexp cascade logic delay 0.4 0.7 0.9 1.0 ns t lad logic array delay 1.5 2.5 3.2 6.0 ns t lac logic control delay 0.6 1.0 1.2 3.5 ns t ioe internal output enable delay 0.0 0.0 00 3.0 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 0.8 1.3 1.8 3.0 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 1.3 1.8 2.3 3.0 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l = 35pf) 5.8 6.3 6.8 5.0 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 4.0 4.0 5.0 7.0 ns
31 atf1504ae(l) 2398b ? 08/01 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac , t ic , t acl and t sexp parameters for macrocells running in the reduced- power mode. t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5v or 3.3v; c l = 35pf) 9.0 9.0 10.0 10 ns t xz output buffer disable delay (c l = 5pf) 4.0 4.0 5.0 6.0 ns t su register setup time 1.3 2.0 2.9 5.0 ns t h register hold time 0.6 1.0 1.3 4.0 ns t fsu register setup time of fast input 1.0 1.5 1.5 2.0 ns t fh register hold time of fast input 1.5 1.5 1.5 2.0 ns t rd register delay 0.7 1.2 1.6 2.0 ns t comb combinatorial delay 0.6 0.9 1.3 2.0 ns t ic array clock delay 1.2 1.9 2.5 6.0 ns t en register enable time 0.6 1.0 1.2 6.0 ns t glob global control delay 1.0 1.5 2.2 2.0 ns t pre register preset time 1.3 2.1 2.9 4.0 ns t clr register clear time 1.3 2.1 2.9 4.0 ns t uim switch matrix delay 1.0 1.7 2.3 2.0 ns t rpa (2) reduced power adder 3.5 4.0 5.0 10 ns ac characteristics atf1504ae(l) (continued) (1) symbol parameter -4 -7 -10 -15 unit min max min max min max min max
32 atf1504ae(l) 2398b ? 08/01 stand-by i cc vs. supply voltage (t a = 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.8 5.0 5.3 5.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. supply voltage (v oh = 2.4v) -50 -40 -30 -20 -10 0 4.0 4.5 5.0 5.5 6.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol = 0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc = 5.0v, t a = 25 c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc = 5.0v, t a = 25 c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd
33 atf1504ae(l) 2398b ? 08/01 input clamp current vs. input voltage (v cc = 5.0v, t a = 35 c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc = 5.0v, t a = 25 c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input curren t (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd
34 atf1504ae(l) 2398b ? 08/01 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd
35 atf1504ae(l) 2398b ? 08/01 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gndint ground pins for the internal device logic gndio ground pins for the i/o pins vccint vcc pins for the internal device logic vccio vcc for the i/o drivers atf1504ae(l) dedicated pinouts dedicated pin 44-lead tqfp 44-lead j-lead 49-ball bga 100-ball bga 100-lead tqfp input/oe2/gclk2 40 2 b4 a5 90 input/gclr 39 1 a3 b5 89 input/oe1 3844a4b688 input/gclk13743a5a687 i/o /gclk3 35 41 c4 c6 85 i/o/pd (1,2) 5, 19 11, 25 d1, g5 e1, h6 12, 42 i/o/tdi (jtag) 1 7 b1 a1 4 i/o/tms (jtag)7 13f1f315 i/o/tck (jtag) 26 32 f7 f8 62 i/o/tdo (jtag) 32 38 b7 a10 73 gndint 16, 36 22, 44 c2, e6 c3, d6, d7, e5, f6, g4, g5, h8 38, 86 gndio 4, 24 10, 30 b5, f4 ? 11, 26, 43, 59, 74, 95 vccint 17, 41 3, 23 b3, e4 d5, g6 39, 91 vccio 9, 29 15, 35 c6, e2 c8, d4, e6, f5, g7, h3 3, 18, 34, 51, 66, 82 n/c - - - b1, b10, c1, c9, c10, d8, e3, e4, h1, h9, h10, j1, j2, j10, k1, k9 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 # of signal pins 36 36 41 68 68 # user i/o pins 32 32 37 64 64
36 atf1504ae(l) 2398b ? 08/01 atf1504ae(l) i/o pinouts mc plc 44-lead plcc 44-lead tqfp 49-ball bga 84-lead plcc 100- ball bga 100- lead tqfp mc plc 44-lead plcc 44-lead tqfp 49-ball bga 84-lead plcc 100- ball bga 100- lead tqfp 1 a 12 6 d2 22 f4 14 33 c 24 18 e5 44 k6 40 2 a - - - 21e21334 c - - - 45j641 3 a/ pd1 11 5 d120e11235 c/ pd2 25 19 g5 46 h6 42 4 a 9 3 d4 18 d2 10 36 c 26 20 f5 48 k7 44 5 a 8 2 c1 17 d1 9 37 c 27 21 g6 49 j7 45 6 a - - - 16 d3 8 38 c - - - 50 h7 46 7a - - -15c2639c - -g751j847 8/ tdi a 7 1 b114a1 4 40 c 2822f652k848 9 a - - b2 12 b2 100 41 c 29 23 d5 54 k10 52 10 a - - - 11 a2 99 42 c - - - 55 j9 54 11 a 6 44 a1 10 a3 98 43 c - - - 56 g9 56 12a---9b39744c---57g1057 13a---8a49645c---58g858 14 a 5 43 a2 6 b4 94 46 c 31 25 e7 60 f9 60 15 a - - - 5 c4 93 47 c - - - 61 f10 61 16 a 4 42 c3 4 c5 92 48/ tck c 3226f762f862 17 b 21 15 g4 41 k5 37 49 d 33 27 d7 63 f7 63 18 b - - e340j53650 d - - - 64e964 19 b 20 14 g3 39 h5 35 51 d 34 28 d6 65 e10 65 20 b 19 13 f3 37 k4 33 52 d 36 30 c7 67 e8 67 21 b 18 12 g2 36 j4 32 53 d 37 31 b6 68 e7 68 22 b - - g135h43154 d - - - 69d969 23 b - - - 34 j3 30 55 d - - - 70 d10 71 24 b 1711f233k329 56/ tdo d 3832b771a1073 25 b 16 10 d3 31 k2 25 57 d 39 33 a7 73 b9 75 26 b - - - 30 h2 23 58 d - - - 74 a9 76 27 b - - - 29 g2 21 59 d - - a6 75 a8 79 28 b - - - 28 g1 20 60 d - - - 76 b8 80 29 b - - - 27 g3 19 61 d - - - 77 a7 81 30 b 14 8 e1 25 f2 17 62 d 40 34 c5 79 b7 83 31 b - - - 24 f1 16 63 d - - - 80 c7 84 32/ tms b 13 7 f1 23 f3 15 64 d/ gclk3 41 35 c4 81 c6 85
37 atf1504ae(l) 2398b ? 08/01 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use commercial product for industrial temperature ranges, de-rate i cc by 15%. atf1504ae(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 4 3 230 atf1504ae-4 ac44 atf1504ae-4 jc44 atf1504ae-4 cc49 atf1504ae-4 ac100 atf1504ae-4 cc100 44a 44j 49c1 100a 100ct1 commercial (0 c to 70 c) 7 4 140 atf1504ae-7 ac44 atf1504ae-7 jc44 atf1504ae-7 cc49 atf1504ae-7 ac100 atf1504ae-7 cc100 44a 44j 49c1 100a 100ct1 commercial (0 c to 70 c) atf1504ae-7 ai44 atf1504ae-7 ji44 atf1504ae-7 ci49 atf1504ae-7 ai100 atf1504ae-7 ci100 44a 44j 49c1 100a 100ct1 industrial (-40 c to +85 c) 10 6 100 atf1504ae-10 ac44 atf1504ae-10 jc44 atf1504ae-10 cc49 atf1504ae-10 ac100 atf1504ae-10 cc100 44a 44j 49c1 100a 100ct1 commercial (0 c to 70 c) atf1504ae-10 ai44 atf1504ae-10 ji44 atf1504ae-10 ci49 atf1504ae-10 ai100 atf1504ae-10 ci100 44a 44j 49c1 100a 100ct1 industrial (-40 c to +85 c) 15 8 77 atf1504ael-15 ac44 atf1504ael-15 jc44 atf1504ael-15 cc49 atf1504ael-15 ac100 atf1504ael-15cc100 44a 44j 49c1 100a 100ct1 commercial (0 c to 70 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 49c1 49-lead, chip scale ball grid array (cbga) 0.8 mm pitch 100a 100-lead, very thin plastic gull wing quad flatpack (tqfp) 100ct1 100-lead, tape ball grid array (tbga) 1.0 mm pitch
38 atf1508ae(l) 2398b ? 08/01 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. dc characteristics atf1508ae(l) (1) symbol parameter condition min typ min unit i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 2 10 a i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 115 ma ind. 135 ma ? itd ? mode com. 1 ma ind. 1 ma i cc2 power supply current, power-down mode v cc = max v in = 0, v cc pd mode 0.1 1 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std mode com. 55 ma ind. 80 ma v il input low voltage -0.3 0.8 v v ih input high voltage 1.7 v ccio +0.3 v v ol output low voltage (ttl) v in = v ih or v il v cc = min, i ol = 8 ma com. 0.45 v ind. 0.45 v output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage -3.3v (ttl) v in = v ih or v il v cc = min, i oh = -2.0 ma 2.4 v output high voltage -3.3v (cmos) v in = v ih or v il v cc = min, i oh = -0.1 ma v ccio -0.2 v power-down ac characteristics atf1508ae(l) (1) symbol parameter -5 -7 -10 -15 unit minmaxminmaxminmaxminmax t ivdh valid 1, i/o before pd high 4.5 7.5 10 15 ns t gvdh valid 1, oe (2) before pd high 4.5 7.5 10 15 ns t cvdh valid 1, clock (2) before pd high 4.5 7.5 10 15 ns t dhix i, i/o don ? t care after pd high 9.0 15 20 25 ns t dhgx oe (2) don ? t care after pd high 9.0 15 20 25 ns t dhcx clock (2) don ? t care after pd high 9.0 15 20 25 ns t dliv pd low to valid i, i/o 1.0 1.0 1.0 1.0 s t dlgv pd low to valid oe, (pin or term) 1.0 1.0 1.0 1.0 s t dlcv pd low to valid clock, (pin or term) 1.0 1.0 1.0 1.0 s t dlov pd low to valid output 1.0 1.0 1.0 1.0 s
39 atf1508ae(l) 2398b ? 08/01 ac characteristics atf1508ae(l) (1) symbol parameter -5 -7 -10 -15 unit minmaxminmaxminmaxminmax t pd1 input or feedback to non-registered output 5 7.5 10 3 ns t pd2 i/o input or feedback to non-registered feedback 5 7.5 10 3 ns t su global clock setup time 3.3 4.9 6.6 11 ns t h global clock hold time 0 0 0 0 ns t fsu global clock setup time of fast input 2.5 3 3 3 ns t fh global clock hold of fast input 0 0 0 1 mhz t cop global clock to output delay 1 3.4 1 5 1 6.6 9 ns t ch global clock high time 2 3 4 5 ns t cl global clock low time 2 3 4 5 ns t asu array clock setup time 1.8 2.8 3.8 5 ns t ah array clock hold time 0.2 0.3 0.3 4 ns t acop array clock output delay 1 4.9 1 7.1 1 9.4 15 ns t ach array clock high time 2 3 4 6 ns t acl array clock low time 2 3 4 6 ns t cnt minimum clock global period 5.2 7.7 10.2 13 ns f cnt maximum internal global clock frequency 193 130 100 77 mhz t acnt minimum array clock period 5.2 7.7 10.2 13 ns f acnt maximum internal array clock frequency 193 130 100 77 mhz f max maximum clock frequency 200 133 100 77 mhz t in input pad and buffer delay 0.7 1 1.4 2 ns t io i/o input pad and buffer delay 0.7 1 1.4 2 ns t fin fast input delay 2.5 3 3.4 2 ns t sexp foldback term delay 2 2.9 3.8 8 ns t pexp cascade logic delay 0.4 0.7 0.9 1 ns t lad logic array delay 1.6 2.4 3.1 6 ns t lac logic control delay 0.7 1 1.3 3.5 ns t ioe internal output enable delay 0 0 0 3 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 0.8 1.2 1.6 3 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 1.3 1.7 2.1 3 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 5.8 6.2 6.6 5 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 4457ns
40 atf1508ae(l) 2398b ? 08/01 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac , t ic , t acl and t sexp parameters for macrocells running in the reduced- power mode. t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 4.5 4.5 5.5 7 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 9 9 10 10 ns t xz output buffer disable delay (c l = 5pf) 4 4 5 6 ns t su register setup time 1.4 2.1 2.9 5 ns t h register hold time 0.6 1 1.3 4 ns t fsu register setup time of fast input 1.1 1.6 1.6 2 ns t fh register hold time of fast input 1.4 1.4 1.4 2 ns t rd register delay 0.8 1.2 1.6 2 ns t comb combinatorial delay 0.5 0.9 1.3 2 ns t ic array clock delay 1.2 1.7 2.2 6 ns t en register enable time 0.7 1 1.3 6 ns t glob global control delay 1.1 1.6 2 2 ns t pre register preset time 1.4 2 2.7 4 ns t clr register clear time 1.4 2 2.7 4 ns t uim switch matrix delay 1.4 2 2.6 2 ns t rpa (2) reduced power adder 4.0 4.0 5 10 ns ac characteristics atf1508ae(l) (continued) (1) symbol parameter -5 -7 -10 -15 unit minmaxminmaxminmaxminmax
41 atf1508ae(l) 2398b ? 08/01 stand-by i cc vs. supply voltage (t a = 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.8 5.0 5.3 5.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. supply voltage (v oh = 2.4v) -50 -40 -30 -20 -10 0 4.0 4.5 5.0 5.5 6.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol = 0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc = 5.0v, t a = 25 c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc = 5.0v, t a = 25 c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd
42 atf1508ae(l) 2398b ? 08/01 input clamp current vs. input voltage (v cc = 5.0v, t a = 35 c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input curren t (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc = 5.0v, t a = 25 c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input curren t (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd
43 atf1508ae(l) 2398b ? 08/01 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd
44 atf1508ae(l) 2398b ? 08/01 oe (1,2) global oe pins. gclr global clear pin. gclk (1,2,3) global clock pins. tdi, tms, tck, tdo jtag pins used for in system programming or boundary-scan testing. gndint ground pins for the internal device logic. gndio ground pins for the i/o drivers. vccint vcc pins for the internal device logic. vccio vcc pins for the i/o drivers. atf1508ae(l) dedicated pinouts dedicated pin 84-pin j-lead 100-pin tqfp 100-ball bga 144-pin tqfp 169-ball bga 256-ball bga input/gclk1 83 87 a6 125 d8 d9 input/gclr 1 89 b5 127 d6 e8 input/oe1 84 88 b6 126 d7 e9 input/oe2/gck2 2 90 a5 128 e7 d8 input/gclk3 81 85 c6 119 a8 f9 i/o pd (1,2) 12, 45 1,41 b1, j6 142, 61 d4, h8 e4, m9 tdi (jtag) 14 4 a1 4 e4 d4 tms (jtag) 23 15 f3 20 j4 j6 tck (jtag) 62 62 f8 89 j10 j11 tdo (jtag) 71 73 a10 104 e10 d13 gndint 42, 82 38,86 d6, g5 52, 57, 124, 129 a7, e8, j7, n7 a8, c9, g9, k8, p9 gndio 7, 19, 32, 47, 59, 72 11, 26, 43, 59, 74, 95 c3, d7, e5, f6, g4, h8 3, 13, 17, 33, 59, 64, 85, 105, 135 a3, a12, e1, f5, f13, h1, h9, j13, n2, n11 a3, b10, c2, d14, f6, g10, h8, j9, k7, l11, m3, p6, p10, r2, r3, t1, t15 vccint 3, 43 39, 91 d5, g6 51, 58, 123, 130 b7, e6, h7, m7 b9, c8, g8, k9, p8 vccio 13, 26, 38, 53, 66, 78 3, 18, 34, 51, 66, 82 c8, d4, e6, f5, g7, h3 24, 50, 73, 76, 95, 115, 144 a2, a11, e13, f1, f9, h5, h13, j1, n3, n12 b3, b5, c14, e15, f11, g3, g7, g15, h9, j8, k10, l3, l6, m15, p14, t2, t3 no connect - - - 1, 2, 12, 19, 34, 35, 36, 43, 46, 47, 48, 49, 66, 75, 90, 103, 108, 120, 121, 122 b5, b6, b8, b9, c5, c6, c7, c8, c9, c10, e2, e3, e11, e12, f2, f3, f11, f12, g1, g3, g11, g12, h2, h3, h11, h12, j2, j3, j11, j12, l4, l5, l6, l7, l8, l9, m5, m6, m8, m9 a1, a2, a4, a5, a6, a7, a9, a10, a11, a12, a13, a14, a15, a16, b1, b2, b4, b6, b7, b8, b11, b12, b13, b14, b15, b16, c1, c3, c4, c6, c11, c13, c15, c16, d1, d2, d3, d15, d16, e1, e2, e3, e14, e16, f1, f2, f15, f16, g1, g2, g14, g16, h1, h2, h15, h16, j1, j2, j15, j16, k1, k2, k3, k14, k15, k16, l1, l2, l15, l16, m1, m14, m16, n1, n2, n3, n14, n15, n16, p1, p2, p3, p4, p12, p13, p15, p16, r1, r4, r5, r6, r7, r8, r9, r11, r12, r13, r14, r15, r16, t4, t5, t6, t8, t9, t10, t11, t12, t13, t14, t16 # of signal pins 68 84 84 100 100 100 # of user i/o pins 64 80 80 96 96 96
45 atf1508ae(l) 2398b ? 08/01 atf1508ae(l) i/o pinouts mc plb 84-pin j-lead 100-pin tqfp 100-ball bga 144-pin tqfp 169-ball bga 256-ball bga mc plb 84-pin j-lead 100-pin tqfp 100-ball bga 144-pin tqfp 169-ball bga 256-ball bga 1a - 2 c1143e5f433c - 25k132k4n4 2a------34c------ 3/ pd1 a 12 1 b1 142 d4 e4 35 c 31 24 j1 31 j5 m4 4a---141b2c536c---30n1m2 5 a 11 100 b2 140 b3 e5 37 c 30 23 h1 29 m1 l4 6 a 10 99 a2 139 c3 d5 38 c 29 22 h2 28 l1 l5 7a------39c------ 8 a 9 98 a3 138 c4 d6 40 c 28 21 g2 27 l2 k5 9 a - 97 b3 137 b4 e6 41 c - 20 g1 26 k3 k4 10a------42c------ 11 a 8 96 a4 136 a4 d7 43 c 27 19 g3 25 g6 k6 12a---134d5c744c---23k2j3 13 a 6 94 b4 133 a5 e7 45 c 25 17 f2 22 h4 j5 14 a 5 93 c4 132 f6 f7 46 c 24 16 f1 21 k1 j4 15a------47c------ 16 a 4 92 c5 131 a6 f8 48/ tms c2315f320j4j6 17 b 22 14 f4 18 d1 j7 49 d 41 37 k5 56 n6 n8 18b------50d------ 19 b 21 13 e2 16 g5 h5 51 d 40 36 j5 55 k7 m8 20 b - - - 15 d2 h3 52 d - - - 54 n5 p7 21 b 20 12 e1 14 g4 h4 53 d 39 35 h5 53 h6 l8 22 b - 10 e3 11 d3 h6 54 d - 33 k4 45 n4 n7 23b------55d------ 24 b 18 9 e4 10 c1 h7 56 d 37 32 j4 44 k6 m7 25 b 17 8 d2 9 c2 g5 57 d 36 31 h4 42 m4 l7 26b------58d------ 27 b 16 7 d1 8 g7 g4 59 d 35 30 j3 41 j6 m6 28b---7b1f360d---40m3p5 29 b 15 6 d3 6 f4 g6 61 d 34 29 k3 39 l3 n6 30 b - 5 c2 5 a1 f5 62 d - 28 j2 38 m2 m5 31b------63d------ 32/ tdi b 14 4 a1 4 e4 d4 64 d 33 27 k2 37 k5 n5
46 atf1508ae(l) 2398b ? 08/01 atf1508ae(l) i/o pinouts mc plb 84-pin j-lead 100-pin tqfp 100-ball bga 144-pin tqfp 169-ball bga 256-ball bga mc plb 84-pin j-lead 100-pin tqfp 100-ball bga 144-pin tqfp 169-ball bga 256-ball bga 65 e 44 40 k6 60 l10 n9 97 g 63 63 f7 91 g13 j10 66e------98g------ 67/ pd2 e 45 41 j6 61 h8 m9 99 g 64 64 e9 92 g10 h12 68 e - - - 62 n8 r10 100 g - - - 93 d13 h14 69 e 46 42 h6 63 k8 l9 101 g 65 65 e10 94 g9 h13 70 e - 44 k7 65 n9 n10 102 g - 67 e8 96 d12 h11 71e------103g------ 72 e 48 45 j7 67 j8 m10 104 g 67 68 e7 97 d11 h10 73 e 49 46 h7 68 m10 l10 105 g 68 69 d9 98 c13 g12 74e------106g------ 75 e 50 47 j8 69 k9 m11 107 g 69 70 d10 99 f10 g13 76 e - - - 70 n10 p11 108 g - - - 100 c12 f14 77 e 51 48 k8 71 k10 n11 109 g 70 71 d8 101 e9 g11 78 e - 49 k9 72 l11 n12 110 g - 72 c9 102 b13 f12 79e------111g------ 80 e 52 50 k10 74 m11 n13 112/ tdo g 71 73 a10 104 e10 d13 81 f - 52 j10 77 m12 m13 113 h - 75 c10 106 a13 f13 82f------114h------ 83 f 54 53 h10 78 j9 l13 115 h 73 76 b10 107 d10 e13 84 f - - - 79 n13 l14 116 h - - - 109 b12 c12 85 f 55 54 h9 80 m13 l12 117 h 74 77 b9 110 d9 e12 86 f 56 55 j9 81 l13 m12 118 h 75 78 a9 111 c11 d12 87f------119h------ 88 f 57 56 g9 82 l12 k12 120 h 76 79 a8 112 b11 d11 89 f - 57 g10 83 k13 k13 121 h - 80 b8 113 b10 e11 90f------122h------ 91 f 58 58 g8 84 g8 k11 123 h 77 81 a7 114 f8 d10 92 f - - - 86 k12 j14 124 h - - - 116 a10 c10 93 f 60 60 f9 87 h10 j12 125 h 79 83 b7 117 f7 e10 94 f 61 61 f10 88 k11 j13 126 h 80 84 c7 118 a9 f10 95f------127h------ 96/ tck f6262f889j10j11 128/ gclk3 h81 85c6119a8f9
47 atf1508ae(l) 2398b ? 08/01 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use commercial product for industrial temperature ranges, de-rate i cc by 15%. atf1508ae(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 5 3 200 atf1508ae-5 jc84 atf1508ae-5 ac100 atf1508ae-5 cc100 atf1508ae-5 ac144 atf1508ae-5 cc169 atf1508ae-5 cc256 84j 100a 100ct1 144aa 169c1 256ct1 commercial (0 c to 70 c) 7 4 133 atf1508ae-7 jc84 atf1508ae-7 ac100 atf1508ae-7 cc100 atf1508ae-7 ac144 atf1508ae-7 cc169 atf1508ae-7 cc256 84j 100a 100ct1 144aa 169c1 256ct1 commercial (0 c to 70 c) atf1508ae-7 ji84 atf1508ae-7 ai100 atf1508ae-7 i100 atf1508ae-7 ai144 atf1508ae-7 ci169 atf1508ae-7 ci256 84j 100a 100ct1 144aa 169c1 256ct1 industrial (-40 c to +85 c) 10 6 100 atf1508ae-10 jc84 atf1508ae-10 ac100 atf1508ae-10 cc100 atf1508ae-10 ac144 atf1508ae-15 cc169 atf1508ae-10 cc256 84j 100a 100ct1 144aa 169c1 256ct1 commercial (0 c to 70 c) atf1508ae-10 ji84 atf1508ae-10 ai100 atf1508ae-10 ci100 atf1508ae-10 ai144 atf1508ae-10 ci169 atf1508ae-10 ci256 84j 100a 100ct1 144aa 169c1 256ct1 industrial (-40 c to +85 c) 15 8 77 atf1508ael-15 jc84 atf1508ael-15 ac100 atf1508ael-15 cc100 atf1508ael-15 ac144 atf1508ael-15 cc169 atf1508ael-15 cc256 84j 100a 100ct1 144a 169c1 256ct1 commercial (0 c to 70 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100a 100-lead, very thin plastic gull wing quad flatpack (tqfp) 100ct1 100-lead, tape ball grid array (tbga) 1.0 mm pitch 144aa 144-lead, low profile plastic gull wing quad flatpack (tqfp) 169c1 169-lead, chip scale ball grid array (cbga) 0.8 mm pitch 256ct1 256-lead, tape ball grid array (tbga) 1.0 mm pitch
48 atf1516ae(l) 2398b ? 08/01 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. dc characteristics atf1516ae(l) (1) symbol parameter condition min typ min unit i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 2 10 a i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 115 ma ind. 135 ma ? itd ? mode com. 1 ma ind. 1 ma i cc2 power supply current, power-down mode v cc = max v in = 0, v cc pd mode 0.1 1 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std mode com. 55 ma ind. 80 ma v il input low voltage -0.3 0.8 v v ih input high voltage 1.7 v ccio +0.3 v v ol output low voltage (ttl) v in = v ih or v il v cc = min, i ol = 8 ma com. 0.45 v ind. 0.45 v output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage -3.3v (ttl) v in = v ih or v il v cc = min, i oh = -2.0 ma 2.4 v output high voltage -3.3v (cmos) v in = v ih or v il v cc = min, i oh = -0.1 ma v ccio -0.2 v power-down ac characteristics atf1516ae(l) (1) symbol parameter -5 -7 -10 -15 unit min max min max min max min max t ivdh valid 1, i/o before pd high 4.5 7.5 10 15 ns t gvdh valid 1, oe (2) before pd high 4.5 7.5 10 15 ns t cvdh valid 1, clock (2) before pd high 4.5 7.5 10 15 ns t dhix i, i/o don ? t care after pd high 9.0 15 20 25 ns t dhgx oe (2) don ? t care after pd high 9.0 15 20 25 ns t dhcx clock (2) don ? t care after pd high 9.0 15 20 25 ns t dliv pd low to valid i, i/o 1.0 1.0 1.0 1.0 s t dlgv pd low to valid oe, (pin or term) 1.0 1.0 1.0 1.0 s t dlcv pd low to valid clock, (pin or term) 1.0 1.0 1.0 1.0 s t dlov pd low to valid output 1.0 1.0 1.0 1.0 s
49 atf1516ae(l) 2398b ? 08/01 ac characteristics atf1516ae(l) (1) symbol parameter -5 -7 -10 -15 unit min max min max min max min max t pd1 input or feedback to non-registered output 5.5 7.5 10 15 ns t pd2 i/o input or feedback to non-registered feedback 5.5 7.5 10 12 ns t su global clock setup time 3.9 5.2 6.9 11 ns t h global clock hold time 0 0 0 0 ns t fsu global clock setup time of fast input 2.5 3 3 3 ns t fh global clock hold of fast input 0 0 0 1 mhz t cop global clock to output delay 1 3.5 1 4.8 1 6.4 9 ns t ch global clock high time 2 3 4 5 ns t cl global clock low time 2 3 4 5 ns t asu array clock setup time 2.0 2.7 3.6 5 ns t ah array clock hold time 0.2 0.3 0.5 4 ns t acop array clock output delay 1 5.4 1 7.3 1 9.7 15 ns t ach array clock high time 2 3 4 6 ns t acl array clock low time 2 3 4 6 ns t cnt minimum clock global period 5.8 7.9 10.5 13 ns f cnt maximum internal global clock frequency 175 125 100 77 mhz t acnt minimum array clock period 5.8 7.9 10.5 13 ns f acnt maximum internal array clock frequency 175 125 100 77 mhz f max maximum clock frequency 200 133 100 77 mhz t in input pad and buffer delay 0.7 0.9 1.2 2 ns t io i/o input pad and buffer delay 0.7 0.9 1.2 2 ns t fin fast input delay 2.4 2.9 3.4 2 ns t sexp foldback term delay 2.1 2.8 3.7 8 ns t pexp cascade logic delay 0.3 0.5 0.6 1 ns t lad logic array delay 1.7 2.2 2.8 6 ns t lac logic control delay 0.8 1.0 1.3 3.5 ns t ioe internal output enable delay 0 0 0 3 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 0.9 1.2 1.6 3 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 1.4 1.7 2.1 3 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 5.9 6.2 6.6 5 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 4.0 4.0 5.0 7 ns
50 atf1516ae(l) 2398b ? 08/01 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac , t ic , t acl and t sexp parameters for macrocells running in the reduced- power mode. t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 4.5 4.5 5.5 7 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 9 9 10 10 ns t xz output buffer disable delay (c l = 5pf) 4 4 5 6 ns t su register setup time 1.5 2.1 2.9 5 ns t h register hold time 0.7 0.9 1.2 4 ns t fsu register setup time of fast input 1.1 1.6 1.6 2 ns t fh register hold time of fast input 1.4 1.4 1.4 2 ns t rd register delay 0.9 1.2 1.6 | 2 ns t comb combinatorial delay 0.5 0.8 1.2 2 ns t ic array clock delay 1.2 1.6 2.1 6 ns t en register enable time 0.8 1.0 1.3 6 ns t glob global control delay 1.0 1.5 2.1 2 ns t pre register preset time 1.6 2.3 3.0 4 ns t clr register clear time 1.6 2.3 3.0 4 ns t uim switch matrix delay 1.7 2.4 3.2 2 ns t rpa reduced power adder (2) 4.0 4.0 5.0 10 ns ac characteristics atf1516ae(l) (continued) (1) symbol parameter -5 -7 -10 -15 unit min max min max min max min max
51 atf1516ae(l) 2398b ? 08/01 stand-by i cc vs. supply voltage (t a = 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.8 5.0 5.3 5.5 supply voltage (v) i cc (a) tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 20.000 40.000 60.000 80.000 100.000 120.000 140.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. supply voltage (v oh = 2.4v) -50 -40 -30 -20 -10 0 4.0 4.5 5.0 5.5 6.0 supply voltage (v) i oh (ma) tbd output sink current vs. supply voltage (v ol = 0.5v) 36 38 40 42 44 46 48 4.0 4.5 5.0 5.5 6.0 supply voltage (v) iol (ma) tbd normalized i cc vs. temp 0.4 0.6 0.8 1.0 1.2 1.4 -40.0 0.0 25.0 75.0 temperature (c) normalized icc tbd supply current vs. input frequency (v cc = 5.0v, t a = 25 c) 0.000 0.200 0.400 0.600 0.800 1.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 frequency (mhz) i cc (ma) tbd output source current vs. output voltage (v cc = 5.0v, t a = 25 c) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma) tbd output sink current vs. output voltage (v cc = 5.0v, t a = 25 c) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) i ol (ma) tbd
52 atf1516ae(l) 2398b ? 08/01 input clamp current vs. input voltage (v cc = 5.0v, t a = 35 c) -120 -100 -80 -60 -40 -20 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input curren t (ma) tbd normalized t pd vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t pd tbd normalized t co vs. vcc 0.8 0.9 1.0 1.1 1.2 1.3 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t co tbd normalized t su vs. vcc 0.8 0.9 1.0 1.1 1.2 4.5 4.8 5.0 5.3 5.5 supply voltage (v) normalized t su tbd input current vs. input voltage (v cc = 5.0v, t a = 25 c) -30 -20 -10 0 10 20 30 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 input voltage (v) input curren t (ua) tbd normalized t pd vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (c) normalized t pd tbd normalized t co vs. temp 0.8 0.9 1.0 1.1 -40.0 0.0 25.0 75.0 temperature (v) normalized t co tbd normalized t su vs. temp 0.8 0.9 1.0 1.1 1.2 -40.0 0.0 25.0 75.0 temperature (c) normalized t co tbd
53 atf1516ae(l) 2398b ? 08/01 delta t pd vs. output loading -2 0 2 4 6 8 0 50 100 150 200 250 300 output loading (pf) delta t pd (ns) tbd delta t pd vs. # of output switching -0.5 -0.4 -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t pd (ns) tbd delta t co vs. output loading 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 50 100 150 200 250 300 number of outputs loading delta t co (ns) tbd delta t co vs. # of output switching -0.3 -0.2 -0.1 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 number of outputs switching delta t co (ns) tbd
54 atf1516ae(l) 2398b ? 08/01 oe (1,2) global oe pins. gclr global clear pin. gclk (1,2,3) global clock pins. tdi, tms, tck, tdo jtag pins used for in system programming or boundary-scan testing. gndint ground pins for the internal device logic. gndio ground pins for the i/o drivers. vccint vcc pins for the internal device logic. vccio vcc pins for the i/o drivers. atf1516ae(l) dedicated pinouts dedicated pin 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga input/gclk1 87 a6 125 184 d9 input/gclr 89 b5 127 182 e8 input/oe1 88 b6 126 183 e9 input/oe2/gck2 90 a5 128 181 d8 input/gclk3 tbd tbd tbd tbd tbd i/o pd (1,2) tbd tbd tbd tbd tbd tdi (jtag) 4 a1 4 176 d4 tms (jtag) 15 f3 20 127 j6 tck (jtag) 62 f8 89 30 j11 tdo (jtag) 73 a10 104 189 d13 gndint 38, 86 d6, g5 52, 57, 124, 129 75, 82, 180, 185 a8, c9, g9, k8, p9 gndio 11, 26, 43, 59, 74, 95 c3, d7, e5, f6, g4, h8 3, 13, 17, 33, 59, 64, 85, 105, 135 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 a3, b10, c2, d14, f6, g10, h8, j9, k7, l11, m3, p6, p10, r2, r3, t1, t15 vccint 39, 91 d5, g6, 51, 58, 123, 130 74, 83, 179, 186 b9, c8, g8, k9, p8 vccio 3, 18, 34, 51, 66, 82 c8, d4, e6, f5, g7, h3 24, 50, 73, 76, 95, 115, 144 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 b3, b5, c14, e15, f11, g3, g7, g15, h9, j8, k10, l3, l6, m15, p14, t2, t3 no connect - - - 1,2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 a1, a2, a6, a12, a13, a14, a15, a16, b1, b2, b15, b16, c1, c15, c16, d1, d3, d15, d16, g1, g16, h15, h16, j1, k1, l1, l2, m1, m16, n1, n16, p1, p2, p15, p16, r1, r14, r15, r16, t7, t8, t10, t11, t14, t16 # of signal pins 84 84 120 164 164 # of user i/o pins 80 80 116 160 160
55 atf1516ae(l) 2398b ? 08/01 atf1516ae(l) i/o pinouts mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga 1 a - c1 - 153 c3 33 c - - 36 108 n4 2a-----34c----- 3a - - 2 154c435c - - 35109p3 4a-----36c----- 5 a - b1 1 159 e5 37 c - - 34 110 n3 6 a - - 143 160 d5 38 c - - - 111 m4 7a-----39c----- 8a 2 - - 161c540c25k132112m2 9 a 1 - - 162 b4 41 c 24 j1 31 113 l4 10a-----42c----- 11 a 100 b2 142 163 a4 43 c 23 h1 30 114 l5 12a-----44c----- 13 a - - 141 164 a5 45 c 22 h2 29 115 k6 14 a 99 a2 140 166 d6 46 c - - - 117 k5 15a-----47c----- 16 a 98 a3 139 167 c6 48 c 21 g2 28 118 k4 17 b - - - 141 f5 49 d 31 h4 44 92 n6 18b-----50d----- 19 b - - 10 142 f2 51 d 30 j3 43 93 t5 20b-----52d----- 21 b - - 9 144 e1 53 d 29 k3 42 95 m6 22 b - - - 145 f4 54 d 28 j2 41 96 r5 23b-----55d----- 24 b 8 d2 8 146 f3 56 d - - 40 97 m5 25 b 7 d1 7 147 e2 57 d - - - 98 p5 26b-----58d----- 27 b 6 d3 6 148 d2 59 d - - 39 99 n5 28b-----60d----- 29 b 5 c2 5 149 e3 61 d - - 38 100 t4 30 b - - - 150 e4 62 d - - - 101 r4 31b-----63d----- 32 b 4 a1 4 151 d4 64 d 27 k2 37 102 p4
56 atf1516ae(l) 2398b ? 08/01 atf1516ae(l) i/o pinouts mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga 65 e - - - 168 b6 97 g - - - 119 k3 66e-----98g----- 67 e - - - 169 e6 99 g - - 27 120 k2 68e-----100g----- 69 e - - 138 170 f7 101 g - - 26 121 j7 70 e - - - 171 e7 102 g - - - 122 h7 71e-----103g----- 72 e 97 b3 137 172 d7 104 g 20 g1 25 123 j5 73 e 96 a4 136 173 c7 105 g 19 g3 23 124 j2 74e-----106g----- 75 e 94 b4 134 175 b7 107 g 17 f2 22 126 j3 76e-----108g----- 77 e 93 c4 133 176 a7 109 g 16 f1 21 127 j4 78 e - - 132 177 f8 110 g - - - 128 h6 79e-----111g----- 80 e 92 c5 131 178 b8 112 g 15 f3 20 129 j6 81 f - - - 130 h5 113 h 37 k5 - 79 m8 82f-----114h----- 83 f - - 19 131 h1 115 h 36 j5 54 80 n8 84f-----116h----- 85 f - - 18 132 h2 117 h - - 53 81 l8 86 f - - - 133 h3 118 h 35 h5 - 84 r7 87f-----119h----- 88f14f416135h4120h - - 4986p7 89f13e215136g6121h - - 4887n7 90f-----122h----- 91f12e114137g5123h - - 4788m7 92f-----124h----- 93f10e312138g2125h33k44689l7 94 f - - - 139 g4 126 h - - - 90 t6 95f-----127h----- 96 f 9 e4 11 140 f1 128 h 32 j4 45 91 r6
57 atf1516ae(l) 2398b ? 08/01 atf1516ae(l) i/o pinouts mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 100-ball tqfp 100-pin bga 144-pin tqfp 208-pin pqfp 256-ball bga 129 i 80 b8 114 197 c11 161 k - - - 38 k11 130i-----162k----- 131 i 81 a7 116 196 b11 163 k 57 g10 82 37 k12 132i-----164k----- 133 i - - 117 195 a11 165 k - - 83 36 k14 134 i - - - 194 f10 166 k - - - 35 k13 135i-----167k----- 136 i - - 118 193 e10 168 k 58 g8 84 34 k15 137 i - - 119 192 a10 169 k - - 86 33 k16 138i-----170k----- 139 i 83 b7 120 190 c10 171 k 60 f9 87 31 j13 140i-----172k----- 141 i 84 c7 121 189 d10 173 k 61 f10 88 30 j14 142 i - - - 188 f9 174 k - - - 29 j12 143i-----175k----- 144 i 85 c6 122 187 a9 176 k 62 f8 89 28 j11 145 j 63 f7 - 27 j15 177 l - - - 78 r8 146j-----178l----- 147 j 64 e9 90 26 j16 179 l - - 55 77 t9 148j-----180l----- 149 j 65 e10 91 25 j10 181 l - - 56 76 r9 150 j - - - 24 h14 182 l - - - 73 n9 151j-----183l----- 152 j - - 92 22 h13 184 l 40 k6 60 71 m9 153 j - - 93 21 h12 185 l 41 j6 61 70 l9 154j-----186l----- 155 j 67 e8 94 20 h11 187 l 42 h6 62 69 r10 156j-----188l----- 157 j - - 96 19 h10 189 l 44 k7 63 68 n10 158 j - - - 18 g11 190 l - - - 67 m10 159j-----191l----- 160 j 68 e7 97 17 g14 192 l 45 j7 65 66 l10
58 atf1516ae(l) 2398b ? 08/01 atf1516ae(l) i/o pinouts mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 100-pin tqfp 100-ball bga 144-pin tqfp 208-pin pqfp 256-ball bga 193 m - - 106 4 b14 225 o - - - 49 r13 194m-----226o----- 195 m 75 c10 107 3 c13 227 o - - 74 48 p13 196m-----228o----- 197 m - - 108 206 b13 229 o - - 75 47 n13 198 m - - - 205 f12 230 o - - - 46 m14 199m-----231o----- 200 m - - 109 204 e12 232 o 52 j10 77 45 m13 201 m 76 b10 110 203 d12 233 o 53 h10 78 44 l13 202m-----234o----- 203 m 77 b9 111 202 c12 235 o 54 h9 79 43 l14 204m-----236o----- 205 m - - - 201 b12 237 o 55 j9 80 42 l12 206 m 78 a9 112 199 e11 238 o - - - 40 l15 207m-----239o----- 208 m 79 a8 113 198 d11 240 o 56 g9 81 39 l16 209 n - - - 16 g13 241 p 46 h7 66 65 r11 210n-----242p----- 211 n 69 d9 98 15 g12 243 p 47 j8 67 64 p11 212n-----244p----- 213 n - - 99 13 f16 245 p 48 k8 68 62 n11 214 n - - - 12 f15 246 p 49 k9 69 61 m11 215n-----247p----- 216 n 70 d10 100 11 f13 248 p - - - 60 t12 217 n - - 101 10 f14 249 p - - 70 59 r12 218n-----250p----- 219 n 71 d8 102 9 e16 251 p - - - 58 m12 220n-----252p----- 221 n 72 c9 103 8 e14 253 p - - 71 57 p12 222 n - - - 7 e13 254 p - - - 56 n12 223n-----255p----- 224 n 73 a10 104 6 d13 256 p 50 k10 72 55 t13
59 atf1516ae(l) 2398b ? 08/01 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use commercial product for industrial temperature ranges, de-rate i cc by 15%. atf1516ae(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 5 4 200 atf1516ae-5 ac100 atf1516ae-5 cc100 atf1516ae-5 ac144 atf1516ae-5 qc208 atf1516ae-5 cc256 100a 100ct1 144aa 208q1 256ct1 commercial (0 c to 70 c) 7 5 133 atf1516ae-7 ac100 atf1516ae-7 cc100 atf1516ae-7 ac144 atf1516ae-7 qc208 atf1516ae-7 cc256 100a 100ct1 144aa 208q1 256ct1 commercial (0 c to 70 c) atf1516ae-7 ai100 atf1516ae-7 ci100 atf1516ae-7 ai144 atf1516ae-7 qi208 atf1516ae-7 ci256 100a 100ct1 144aa 208q1 256ct1 industrial (-40 c to +85 c) 10 6.5 100 atf1516ae-10 ac100 atf1516ae-10 cc100 atf1516ae-10 ac144 atf1516ae-10 qc208 atf1516ae-10 cc256 100a 100ct1 144aa 208q1 256ct1 commercial (0 c to 70 c) atf1516ae-10 ai100 atf1516ae-10 ci100 atf1516ae-10 ai144 atf1516ae-10 qi208 atf1516ae-10 ci256 100a 100ct1 144aa 208q1 256ct1 industrial (-40 c to +85 c) 15 8 77 atf1508ael-15 ac100 atf1508ael-15 cc100 atf1508ael-15 ac144 atf1508ael-15 qc208 atf1508ael-15 cc256 100a 100ct1 144aa 208q1 256ct1 commercial (0 c to 70 c) package type 100a 100-lead, very thin plastic gull wing quad flatpack (tqfp) 100ct1 100-ball, tape ball grid array (tbga) 1.0 mm pitch 144aa 144-lead, low profile plastic gull wing quad flatpack (tqfp) 208q1 208-lead, plastic quad flatpack (pqfp) 256ct1 256-ball, tape ball grid array (tbga) 1.0 mm pitch
60 atf1532ae(l) 2398b ? 08/01 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. dc characteristics atf1532ae(l) (1) symbol parameter condition min typ min unit i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 2 10 a i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 115 ma ind. 135 ma ? itd ? mode com. 1 ma ind. 1 ma i cc2 power supply current, power-down mode v cc = max v in = 0, v cc pd mode 0.1 1 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std mode com. 55 ma ind. 80 ma v il input low voltage -0.3 0.8 v v ih input high voltage 1.7 v ccio + 0.3 v v ol output low voltage (ttl) v in = v ih or v il v cc = min, i ol = 8 ma com. 0.45 v ind. 0.45 v output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage -3.3v (ttl) v in = v ih or v il v cc = min, i oh = -2.0 ma 2.4 v output high voltage -3.3v (cmos) v in = v ih or v il v cc = min, i oh = -0.1 ma v ccio - 0.2 v power-down ac characteristics atf1532ae(l) (1) symbol parameter -7 -10 -12 -15 unit minmaxminmaxminmaxminmax t ivdh valid 1, i/o before pd high 7.5 10 12 15 ns t gvdh valid 1, oe (2) before pd high 7.5 10 12 15 ns t cvdh valid 1, clock (2) before pd high 7.5 10 12 15 ns t dhix i, i/o don ? t care after pd high 15 20 22 25 ns t dhgx oe (2) don ? t care after pd high 15 20 22 25 ns t dhcx clock (2) don ? t care after pd high 15 20 22 25 ns t dliv pd low to valid i, i/o 1.0 1.0 1.0 1.0 s t dlgv pd low to valid oe, (pin or term) 1.0 1.0 1.0 1.0 s t dlcv pd low to valid clock, (pin or term) 1.0 1.0 1.0 1.0 s t dlov pd low to valid output 1.0 1.0 1.0 1.0 s
61 atf1532ae(l) 2398b ? 08/01 ac characteristics atf1532ae(l) (1) symbol parameter -7 -10 -12 -15 unit min max min max min max min max t pd1 input or feedback to non-registered output 7.5 10 12 15 ns t pd2 i/o input or feedback to non-registered feedback 7.5 10 12 12 ns t su global clock setup time 5.6 7.6 9.1 11 ns t h global clock hold time 0 0 0 0 ns t fsu global clock setup time of fast input 3 3 3 3 ns t fh global clock hold of fast input 0 0 0 1 mhz t cop global clock to output delay 1 4.7 1 6.3 1 7.5 9 ns t ch global clock high time 3 4 5 5 ns t cl global clock low time 3 4 5 5 ns t asu array clock setup time 2.5 3.5 4.1 5 ns t ah array clock hold time 0.2 0.3 0.4 4 ns t acop array clock output delay 1 7.8 1 10.4 1 12.5 15 ns t ach array clock high time 3 4 5 6 ns t acl array clock low time 3 4 5 6 ns t cnt minimum clock global period 8.6 11.5 13.9 13 ns f cnt maximum internal global clock frequency 120 90 75 70 mhz t acnt minimum array clock period 8.6 11.5 13.9 13 ns f acnt maximum internal array clock frequency 120 90 75 70 mhz f max maximum clock frequency 133 100 80 66 mhz t in input pad and buffer delay 0.7 0.9 1.0 2 ns t io i/o input pad and buffer delay 0.7 0.9 1.0 2 ns t fin fast input delay 3.1 3.6 4.1 2 ns t sexp foldback term delay 2.7 3.5 4.4 8 ns t pexp cascade logic delay 0.4 0.5 0.6 1 ns t lad logic array delay 2.2 2.8 3.5 6 ns t lac logic control delay 1.0 1.3 3.5 3.5 ns t ioe internal output enable delay 0 0 0 3 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 1.0 1.5 1.7 3 ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 1.5 2.0 2.2 3 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 6.0 6.5 6.7 5 ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5v; c l = 35pf) 4557ns
62 atf1532ae(l) 2398b ? 08/01 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac , t ic , t acl and t sexp parameters for macrocells running in the reduced- power mode. t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35pf) 4.5 5.5 5.5 7 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5v or 3.3v; c l =35pf) 9101010ns t xz output buffer disable delay (c l = 5pf) 4 5 5 6 ns t su register setup time 2.1 3.0 3.5 5 ns t h register hold time 0.6 0.8 1.0 4 ns t fsu register setup time of fast input 1.6 1.6 1.6 2 ns t fh register hold time of fast input 1.4 1.4 1.4 2 ns t rd register delay 1.3 1.7 2.1 2 ns t comb combinatorial delay 0.6 0.8 1.0 2 ns t ic array clock delay 1.8 2.3 2.9 6 ns t en register enable time 1.0 1.3 1.7 6 ns t glob global control delay 1.7 2.2 2.7 2 ns t pre register preset time 1.0 1.4 1.7 4 ns t clr register clear time 1.0 1.4 4.8 4 ns t uim switch matrix delay 3.0 4.0 4.8 2 ns t rpa (2) reduced power adder 4.5 5.0 5.0 10 ns ac characteristics atf1532ae(l) (continued) (1) symbol parameter -7 -10 -12 -15 unit min max min max min max min max
63 atf1532ae(l) 2398b ? 08/01 oe (1,2) global oe pins. gclr global clear pin. gclk (1,2,3) global clock pins. tdi, tms, tck, tdo jtag pins used for in system programming or boundary-scan testing. gndint ground pins for the internal device logic. gndio ground pins for the i/o drivers. vccint vcc pins for the internal device logic. vccio vcc pins for the i/o drivers. atf1532ae(l) dedicated pinouts dedicated pin 144-pin tqfp 208-pin pqfp 256-ball bga input/gclk1 125 184 d9 input/gclr 127 182 e8 input/oe1 126 183 e9 input/oe2/gck2 128 181 d8 input/gclk3 tbd tbd tbd i/o pd (1,2) tbd tbd tbd tdi (jtag) 4 176 d4 tms (jtag) 20 127 j6 tck (jtag) 89 30 j11 tdo (jtag) 104 189 d13 gndint 52, 57, 124, 129 75, 82, 180, 185 a8, c9, g9, k8, p9 gndio 3, 13, 17, 33, 59, 64, 85, 105, 135 14, 32, 50, 51, 94, 116, 134, 152, 158, 200 a3, b10, c2, d14, f6, g10, h8, j9, k7, l11, m3, p6, p10, r2, r3, t1, t15 vccint 51, 58, 123, 130 74, 83, 179, 186 b9, c8, g8, k9, p8 vccio 24, 50, 73, 76, 95, 115, 144 5, 23, 41, 63, 85, 105, 107, 125, 143, 165, 191, 207 b3, b5, c14, e15, f11, g3, g7, g15, h9, j8, k10, l3, l6, m15, p14, t2, t3 no connect - - - # of signal pins 120 176 212 # of user i/o pins 116 172 206
64 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 1 a 134 173 d7 33 c 142 163 e4 2a---34c--- 3a---35c--- 4a---36c--- 5 a - - c7 37 c 141 164 c5 6a---38c--- 7a---39c--- 8a---40c--- 9 a - 175 b7 41 c 140 166 a5 10a---42c--- 11 a 133 176 a7 43 c - 167 d5 12a---44c--- 13a---45c--- 14 a 132 177 f8 46 c 139 168 e5 15a---47c--- 16 a 131 178 b8 48 c - - e6 17 b - 169 d6 49 d 2 - b2 18b---50d--- 19b---51d--- 20b---52d--- 21 b 138 170 c6 53 d 1 - a2 22b---54d--- 23b---55d--- 24b---56d--- 25 b 137 171 b6 57 d - 159 b4 26b---58d--- 27 b 136 172 a6 59 d - 160 a4 28b---60d--- 29b---61d--- 30 b - - f7 62 d - 161 c4 31b---63d--- 32 b - - e7 64 d 143 162 c3
65 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 65 e - - e3 97 g - - h6 66e---98g--- 67 e 7 153 c1 99 g 15 141 g5 68e---100g--- 69 e - - b1 101 g 14 142 g4 70e---102g--- 71e---103g--- 72e---104g--- 73 e - 154 a1 105 g - 144 g4 74e---106g--- 75 e 6 155 d2 107 g - 145 g1 76e---108g--- 77e---109g--- 78 e 5 156 d3 110 g 12 146 g6 79e---111g--- 80 e 4 157 d4 112 g - - f5 81 f - 147 f2 113 h 19 135 j1 82f---114h--- 83 f - 148 f3 115 h - 136 h7 84f---116h--- 85 f 11 149 f1 117 h 18 137 h5 86f---118h--- 87f---119h--- 88f---120h--- 89 f - - f4 121 h - - h2 90f---122h--- 91 f 10 150 e1 123 h - 138 h3 92f---124h--- 93f---125h--- 94 f 9 151 d1 126 h - 139 h1 95f---127h--- 96 f 8 - e2 128 h 16 140 h4
66 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 129 i - - k1 161 k 29 115 n4 130 i - - - 162 k - - - 131 i - 129 j7 163 k - 117 m2 132 i - - - 164 k - - - 133 i 20 130 j6 165 k - 118 m1 134 i - - - 166 k - - - 135 i - - - 167 k - - - 136 i - - - 168 k - - - 137 i - 131 j5 169 k 28 119 m4 138 i - - - 170 k - - - 139 i - - j4 171 k - - m5 140 i - - - 172 k - - - 141 i - - - 173 k - - - 142 i - 132 j3 174 k - 120 l5 143 i - - - 175 k - - - 144 i - 133 j2 176 k 27 121 l4 145 j - 122 l2 177 l 34 109 r1 146 j - - - 178 l - - - 147 j - - l1 179 l - - - 148 j - - - 180 l - - - 149 j 26 123 k6 181 l 32 110 p2 150 j - - - 182 l - - - 151 j - - - 183 l - - - 152 j - - - 184 l - - - 153 j 25 124 k5 185 l - 111 n3 154 j - - - 186 l - - - 155 j 23 126 k4 187 l - 112 n2 156 j - - - 188 l - - - 157 j - - - 189 l - - - 158 j 22 127 k3 190 l 31 113 p1 159 j - - - 191 l - - - 160 j 21 128 k2 192 l 30 114 n1
67 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 193 m - 101 p5 225 o 47 88 r7 194 m - - - 226 o - - - 195 m - - - 227 o 46 89 p7 196 m - - - 228 o - - - 197 m - 102 n5 229 o 45 90 t7 198 m - - - 230 o - - - 199 m - - - 231 o - - - 200 m - - - 232 o - - - 201 m 37 103 t4 233 o - 91 l8 202 m - - - 234 o - - - 203 m - 104 r4 235 o 44 92 n7 204 m - - - 236 o - - - 205 m - - - 237 o - - - 206 m 36 106 p4 238 o - - m7 207 m - - - 239 o - - - 208 m 35 108 p3 240 o 43 93 l7 209 n 42 95 r6 241 p 54 79 m9 210 n - - - 242 p - - - 211n---243p--- 212 n - - - 244 p - - - 213 n 41 96 t6 245 p - 80 l9 214 n - - - 246 p - - - 215 n - - - 247 p - - - 216 n - - - 248 p - - - 217 n 40 97 n6 249 p 53 81 r8 218 n - - - 250 p - - - 219 n 39 98 m6 251 p - 84 t8 220 n - - - 252 p - - - 221 n - - - 253 p - - - 222 n - 99 r5 254 p 49 86 n8 223 n - - - 255 p - - - 224 n 38 100 t5 256 p 48 87 m8
68 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 257 q 55 78 n9 289 s 66 62 k11 258 q - - - 290 s - - - 259 q - - - 291 s - - - 260 q - - - 292 s - - - 261 q - 77 t9 293 s 67 61 m12 262 q - - - 294 s - - - 263 q - - - 295 s - - - 264 q - - - 296 s - - - 265 q 56 76 r9 297 s 68 60 n12 266 q - - - 298 s - - - 267 q - 73 l10 299 s 69 59 t12 268 q - - - 300 s - - - 269 q - - - 301 s - - - 270 q 60 71 m10 302 s - 58 r12 271 q - - - 303 s - - - 272 q 61 70 n10 304 s 70 57 t13 273 r 62 69 r10 305 t - 56 p12 274 r - - - 306 t - - - 275 r 63 68 t10 307 t - - - 276 r - - - 308 t - - - 277 r - 67 m11 309 t - 55 t14 278 r - - - 310 t - - - 279r---311t--- 280 r - - - 312 t - - - 281 r - 66 n11 313 t 71 54 p13 282 r - - - 314 t - - - 283 r 65 65 p11 315 t 72 53 r13 284 r - - - 316 t - - - 285 r - - - 317 t - - - 286 r - - r11 318 t - 52 r14 287 r - - - 319 t - - - 288 r - 64 t11 320 t 74 49 r15
69 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 321 u 75 48 p15 353 w 82 35 l16 322 u - - - 354 w - - - 323 u - - - 355 w - - l13 324 u - - - 356 w - - - 325 u - 47 n15 357 w 83 34 l12 326 u - - - 358 w - - - 327 u - - - 359 w - - - 328 u - - - 360 w - - - 329 u - 46 t16 361 w 84 33 k12 330 u - - - 362 w - - - 331 u - 45 r16 363 w 86 31 k14 332 u - - - 364 w - - - 333 u - - - 365 w - - - 334 u 77 44 p16 366 w 87 30 k15 335 u - - - 367 w - - - 336 u 78 43 n14 368 w 88 29 k16 337 v 79 42 n16 369 x 89 j11 338 v - - - 370 x - - - 339 v 80 40 m14 371 x - 28 j12 340 v - - - 372 x - - - 341 v - 39 n13 373 x - 27 j13 342 v - - - 374 x - - - 343 v - - - 375 x - - - 344 v - - - 376 x - - - 345 v 81 38 m16 377 x - 26 j14 346 v - - - 378 x - - - 347 v - - m13 379 x - - j15 348 v - - - 380 x - - - 349 v - - - 381 x - - - 350 v - 37 l14 382 x - 25 k13 351 v - - - 383 x - - - 352 v - 36 l15 384 x 90 24 j16
70 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 385 y 91 22 h10 417 aa - 10 f14 386 y - - - 418 aa - - - 387 y - 21 h11 419 aa - 9 f15 388 y - - - 420 aa - - - 389 y 92 20 h12 421 aa 98 8 f16 390 y - - - 422 aa - - - 391 y - - - 423 aa - - - 392 y - - - 424 aa - - - 393 y - - h15 425 aa - - e12 394 y - - - 426 aa - - - 395 y - 19 h16 427 aa 99 7 e13 396 y - - - 428 aa - - - 397 y - - - 429 aa - - - 398 y - 18 h14 430 aa 100 6 e14 399 y - - - 431 aa - - - 400 y 93 17 h13 432 aa 101 - e16 401 z - - g12 433 bb - - d16 402 z - - - 434 bb - - - 403 z - 16 g13 435 bb 102 4 c16 404 z - - - 436 bb - - - 405 z 94 15 g14 437 bb - - b16 406 z - - - 438 bb - - - 407 z - - - 439 bb - - - 408 z - - - 440 bb - - - 409 z 96 13 g16 441 bb - 3 a16 410 z - - - 442 bb - - - 411 z - 12 g11 443 bb 103 2 d15 412 z - - - 444 bb - - - 413 z - - - 445 bb - - - 414 z 97 11 f12 446 bb 104 1 d13 415 z - - - 447 bb - - - 416 z - - f13 448 bb 106 208 c15
71 atf1532ae(l) 2398b ? 08/01 atf1532ae(l) i/o pinouts mc plb 144-pin tqfp 208-pin pqfp 256-ball bga mc plb 144-pin tqfp 208-pin pqfp 256-ball bga 449 cc - - b15 481 ee - 196 d11 450 cc - - - 482 ee - - - 451 cc - - - 483 ee - - - 452 cc - - - 484 ee - - - 453 cc 107 - a15 485 ee 113 195 c11 454 cc - - - 486 ee - - - 455 cc - - - 487 ee - - - 456 cc - - - 488 ee - - - 457 cc 108 206 b14 489 ee 114 194 a11 458 cc - - - 490 ee - - - 459 cc - 205 a14 491 ee 116 193 b11 460 cc - - - 492 ee - - - 461 cc - - - 493 ee - - - 462 cc - 204 b13 494 ee 117 - f10 463 cc - - - 495 ee - - - 464 cc 109 203 a13 496 ee - - e10 465 dd - 202 c13 497 ff 118 192 d10 466 dd - - - 498 ff - - - 467 dd - - - 499 ff - - - 468 dd - - - 500 ff - - - 469 dd 110 201 d12 501 ff - - c10 470 dd - - - 502 ff - - - 471 dd - - - 503 ff - - - 472 dd - - - 504 ff - - - 473 dd 111 199 c12 505 ff 119 190 a10 474 dd - - - 506 ff - - - 475 dd - 198 b12 507 ff 120 189 j10 476 dd - - - 508 ff - - - 477 dd - - - 509 ff - - - 478 dd 112 197 a12 510 ff 121 188 f9 479dd---511ff--- 480 dd - - e11 512 ff 122 187 a9
72 atf1532ae(l) 2398b ? 08/01 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use commercial product for industrial temperature ranges, de-rate i cc by 15%. atf1532ae(l) ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 7 5 133 atf1532ae-7 ac144 atf1532ae-7 qc208 atf1532ae-7 cc256 144aa 208q1 256ct1 commercial (0 c to 70 c) 10 6.5 100 atf1532ae-10 ac144 atf1532ae-10 qc208 atf1532ae-10 cc256 144aa 208q1 256ct1 commercial (0 c to 70 c) atf1532ae-10 ai144 atf1532ae-10 qi208 atf1532ae-10 ci256 144aa 208q1 256ct1 industrial (-40 c to +85 c) 12 7.5 80 atf1532ae-12 ac144 atf1532ae-12 qc208 atf1532ae-12 cc256 144aa 208q1 256ct1 commercial (0 c to 70 c) atf1532ae-12 ai144 atf1532ae-12 qi208 atf1532ae-12 ci256 144aa 208q1 256ct1 industrial (-40 c to +85 c) 15 8 77 atf1508ael-15 ac144 atf1508ael-15 cc208 atf1508ael-15 cc256 144a 169q1 256ct1 commercial (0 c to 70 c) package type 144a 144-lead, very thin plastic gull wing quad flatpack (tqfp) 208q 208-ball, plastic quad flatpack (pqfp) 256ct1 256-lead, tape ball grid array (tbga) 1.0 mm pitch
? atmel corporation 2001. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel product operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-7658-3000 fax (33) 4-7658-3480 atmel heilbronn theresienstrasse 2 pob 3535 d-74025 heilbronn, germany tel (49) 71 31 67 25 94 fax (49) 71 31 67 24 23 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 0 2 40 18 18 18 fax (33) 0 2 40 18 19 60 atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-4253-6000 fax (33) 4-4253-6001 atmel smart card ics scottish enterprise technology park east kilbride, scotland g75 0qr tel (44) 1355-357-000 fax (44) 1355-242-743 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. logic doubling ? is the trademark of atmel. other terms and product names may be the trademarks of others. 2398b ? 08/01/xm

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